(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to active pixel sensor (APS) technology.
(2) Description of Prior Art
There are two major categories of APS: active CMOS pixels and active bipolar pixels. Conventional active CMOS pixels are discussed by Fossum in paper BI, Proceedings of International Conference on VLSIxe2x80x94technology, systems and applications; Taipei, 1997. Active bipolar pixels are described in Mead, U.S. Pat. No. 5,260,592 and in Chi et al., paper B2, Proceedings of International Conference on VLSIxe2x80x94technology, systems and applications; Taipei, 1997. The active bipolar pixel size is about 5 times smaller than the active CMOS pixel, but there are blooming and image-lag limitations.
A popular conventional active pixel based on CMOS, shown in FIG. 1, contains one photo-diode and three n-channel MOS transistors (for reset, source follower, and row access). The xe2x80x9creset transistorxe2x80x9d, 10, is used for resetting the potential of the floating-node of photo-diode 12 to Vcc. The floating-node of the photo-diode is connected to the gate of xe2x80x9csource followerxe2x80x9d 14, where its conductance is modulated by the floating-node potential. After reset operation, the potential of photo-diode is modulated (decreasing) by accumulating electrons generated by image light (or photons) during the xe2x80x9cimage integrationxe2x80x9d period. After turning on the row access transistor, 16, Vo is read out (one VT below the floating-node potential) as the output of the image signal. The output is essentially linear with the photo-signal (i.e. floating-node potential). In short, one basic CMOS pixel needs one diode (for light collection) and 3 transistors for implementing functions of reset, image integration, and read (or sensing).
A popular conventional bipolar active pixel, shown in FIGS. 2a and 2b, contains a vertical bipolar (npn) transistor, 8o, with a capacitor, 82, coupled to the base, as is indicated in FIG. 2b. It has simple layout and can be fabricated by typical CMOS technology processing (FIG. 2b). The p base, 18, to n+ emitter, 20, junction is used for collecting image light (or photons), and the n-well region 26 is the transistor""s collector region. The base coupled capacitor is simply a gate capacitor formed between the poly, 22, and the p-base, 18, across the gate oxide layer, 24. It is used for switching the base potential toward reverse-bias for xe2x80x9cimage integrationxe2x80x9d and forward-bias with respect to the emitter for xe2x80x9creadxe2x80x9d operation. Region 28 is a dielectric layer, region 30 is dielectric spacers as used in LDD structures of CMOS transistors and 32 is a metal region providing contact to the emitter. The charge generated by photons during image integration period is amplified by the bipolar action during a read (or sensing) period and collected by the column (charge) sense amplifier (SA). The output of such a bipolar active pixel, which is the bipolar amplified charge generated by photons, is also essentially linear with the photo-signal (i.e. the floating p-base potential. The active bipolar pixel is known to have more image-lag and blooming limitations and is more useful for high resolution still photography. As a comparison, the CMOS active pixel has much less blooming and image-lag problems although its pixel size is about 5 times larger than that of an active bipolar pixel.
Chi et al., in U.S. Pat. Nos. 5,587,596 and 5,68,243, describe single transistor active pixel sensor cells that provide automatic anti-blooming and wide dynamic range, and reduce the size of conventional active pixel cells. U.S. Pat. No. 5,952,686 to Chou et al. provides a salient integration mode active pixel sensor that is compatible with CMOS fabrication processes. A color active pixel sensor cell with oxide color filters is disclosed in U.S. Pat. No. 5,945,722 to Tsui et al. Layouts that increase the photon induced current of metal oxide semiconductor image sensors are described by Yang et al. in U.S. Pat. No. 6,147,372.
It is a primary objective of the invention to provide a new type of active pixel structure that uses a gated junction""s gate-induced-drain-leakage (GIDL) current, which is triggered by band-to-band tunneling, as the sensing mechanism. It is also a primary objective to provide a method to fabricate these new structures.
The new pixel has one photo-diode for light collection, usually the larger in area, and one floating-gated output diode for output GIDL current to a SA for sensing the current. The floating-gate (poly-1) is connected to the floating-node of the photo-diode. Thus, the potential of the floating-gate (and floating-node) represents the image photo-signal, which has exponential effect on the output GIDL current to SA. A control-gate (poly-2), which is coupled to the floating-gate, provides switching capabilities to all operations (for reset, integration, and read) of the new pixel. The new pixel has small size, good anti-blooming and image-lag performance, and, for the first time, is capable of exponential output (i.e. GIDL current) with respect to the photo-signal (i.e. the floating-node potential).
A structure of a new active pixel sensor cell formed in a semiconductor substrate is disclosed. An n-type region is formed in the substrate extending to the surface. Two p+ regions are formed in the n-type region, both extending to the surface and covering almost all the active area of the new active pixel sensor cell. The p+ region forming the p+ node of the photodiode has a substantially larger surface area than the p+ region forming the p+ node of the output diode. Isolation regions are formed over those portions of the new active pixel cell periphery that will not be adjacent to other new active pixel sensor cells. A polysilicon floating gate is disposed over a dielectric layer formed over the surface. The floating gate overlaps portions of both p+ regions and the floating-gate is connected to photodiode p+ region by a conducting region passing through the dielectric layer. A control gate is disposed over the photodiode p+ region and over the floating-gate and is separated from the photodiode p+ region and the floating-gate by dielectric layers. A metal layer, disposed over a dielectric layer, is connected to the output diode p+ region by a conductive region passing through the dielectric layers.